1. Field of the Invention
This invention relates to MOSFET SRAM cells and more particularly to a method of manufacturing a Vertical MOSFET SRAM cell and the structure provided thereby.
2. Description of Related Art
Use of vertical channel MOSFETs enables precise control of channel length, for high performance applications.
U.S. Pat. No. 6,477,080 of Noble for “Circuits and Methods for a Static Random Access Memory Using Vertical Transistors” describes a vertical SRAM device with floating bodies of the FET devices in the SRAM circuit. The patent also states as follows:
“The n-channel and p-channel transistors of memory cell . . . have gates that are formed of n+ and p+ polysilicon, respectively. The polysilicon gates in an inverter are coupled together with a gate contact that is formed of a refractory metal so as to provide a dual work function feature for desired surface channel characteristics in each transistor in the inverter. It is noted that the device bodies of the transistors in memory cell . . . are isolated from each other and the substrate such that the transistors exhibit semiconductor-on-insulator characteristics. Thus, the transistors may be fully depleted, floating body devices and no CMOS wells are needed for isolation.
“However, a body contact can be included using the technique of U.S. application Ser. No. 08/889,396, . . . ”, (now U.S. Pat. No. 5,909,618 of Forbes et al. entitled “Memory Cell with Vertical Transistor and Buried Word and Body Lines”).
We believe that there is a problem with a structure with individual floating body devices the components of the cross coupled inverters of an SRAM circuit. The problem is that with individual floating body devices the devices suffer from Vt mismatch, which means that the values of matched pull-up transistor pairs and matched pull-down transistor pairs will float to divergent Vt values due to body charging. In addition to potential loss of data due to errors caused by highly divergent Vt values, in less serious cases of Vt mismatch the result will be a compromise in the sensitivity of the cell. When the Vt values of the matched transistor pairs diverge, there is a significant risk of loss of data. Thus, the idea of external connections to the bodies of the FET devices are an alternative which could overcome the Vt mismatch problem.
The alternative of providing external body contacts is undesirable in that valuable surface area of the SRAM structure will be required to locate the contacts. Accordingly, it is believed that there is a need to find an alternative to either of the suggestions made by Noble.
While the Noble patent recognizes that the floating bodies of the FET devices is a concern. the citation of the application describing contacts to the bodies such that they can be held at a specific potential would exact a price would have to be paid in terms of extra cell area and process complexity. We recognize that by tying the bodies of the pull-downs together, and the pull-ups together, Vt matching is achieved.
The general direction of the industry is to scale aggressively the minimal lithographic dimension F (this is what one can print with photolithography). At present, a typical integrated circuit (IC) has F of 0.18 μm (1800 Å), while a high performance circuit has a cutting edge F of 0.13 μm (1300A), while processes and structures for 0.1 μm (1000 Å) F technology are being in development. Another general trend in the semiconductor industry is the reduction of relative area of various memory cells, that is a planar SRAM cell in 0.18 μm technology is measured 120–140F2 while in 0.13 technology it is smaller 100–120F2. It is highly desirable to have memory cells that can be scaled to the technology with F<0.1 μm without a substantial penalty in the relative area.
Noble's preferred embodiment is given for F=0.3 μm (column 5, line 15). There could be some features in the structure that have sublithographic dimensions. Deposition and etching techniques allows for the creation of such sublithographic features. For instance, in an extreme case, both deposition and etching can be controlled with a precision of one atomic monolayer (which is about 1–5 Å depending on particular chemical bonds). In practice, the control of these features are within 10% of the targeted deposition and/or removal. That is, one has available deposition and etching techniques that can routinely and reliably create/remove layers of 10–50 Å thick. A combination of such deposition techniques can be used to create more elaborate sublithographic structures. For instance, a borderless contact is defined by two (or more) sublithographic spacers formed on the walls of narrow lithography-defined 1F-wide trench. The material in between the spacers is etched selectively to the material of spacers, thus providing an opening with the width of 1F minus 2× spacer thickness.
In Noble's patent, the spacer thickness is ¼F and the opening thickness is ½F. In general, in order to make an elaborate sublithographic structure such as a borderless contact one has to use a none obvious combination of materials and process steps that would translate the precision of deposition and etching techniques into the useful three-dimensional structure. Often that none-obvious combination of materials and process steps may results in drawbacks and/or incompatibility with other structures.
The Noble patent teaches a borderless (sublithographic) structure between conductors that utilizes (a) formation of sublithographic overhang SiN spacers, (b) removal of one of the spacers with the aid of a photolithographic mask, (c) creating a one-sided sublithographic trench, (d) filling the trench with intrinsic polysilicon, (e) etching the oxide cap selective to the intrinsic polysilicon to create a space for the conductor. Note that the conductors are separated by the sublithographic (˜¼F) layer of intrinsic polysilicon. The intrinsic silicon is then partially removed in a layer and left in the other portions of the circuit as 530. The intrinsic polysilicon is not a good insulator material. It should be very thick in order to effectively isolate conductors. Even at F=0.3 μm , the polysilicon layer of 750 Å can hardly isolate the metallic conductors due to the residual doping and dopant outdiffusion from heavily doped source/drain. At F=0.1 μm, the polysilicon spacer becomes only 250 Å and surely result in the shorted structure.
In our case, the structure does not have any limitation due to the dopant outdiffusion and/or residual doping level. In fact, various conductor layers will isolated even at a technology node with F=0.03 μm. Between 0.3 μm and 0.03 μmm is two (2) orders of magnitude.
U.S. Pat. No. 5,909,618 of Forbes et al. entitled “Memory Cell with Vertical Transistor and Buried Word and Body Lines” describes and shows (FIG. 4 thereof) a DRAM device with a body line (208) juxtaposed with a pair of body regions (214) that forms a very complicated body contact structure. The body line (208) which provides mechanical and electrical body contacts to vertical sidewalls (223) of body regions (130) is formed on top of what appears to be a buried isolation layer (400). In order simply to make contact to the body regions (214) of two adjacent devices Forbes forms a recessed spacer (218) along with isolation layer (400) is provided for isolation of the body line (208) from the source region (212), and then forms the body line (208). Another complexity of Forbes is that the body line (208) is recessed so that it will not contact to the drain layer (216).
U.S. Pat. No. 6,133,608 of Flaker, et al. for “SOI-Body Selective Link Method and Apparatus”, which does not relate to vertical transistors, describes a planar FET SRAM silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. A conductive body link is formed in the silicon layer of the SOI wafer over a silicon oxide isolation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.
The Flaker et al. patent states as follows: “For SOI devices, since all the bodies are floating, the initial body potential can range from near ground to near Vdd (when considering both NFETs and PFETs whose source may not necessarily be grounded or tied to Vdd). As referred to herein above, this produces a large Vt mismatch. This mismatch can slow down sensing (i.e., a slower set pulse is required) or it results in a complete failure to set the latch in a proper direction. The Flaker et al. patent also states as follows “By linking the bodies of pairs of devices, much of the performance advantage of SOI relative to bulk CMOS is maintained (e.g., dynamic Vt lowering). On the other hand, if all bodies were tied together, the charge state of any one device would not significantly affect the body potential. In addition, in the instance if all bodies were tied together, performance would approach a performance of bulk devices (except for reduced junction capacitance).” The problems with the Flaker et al. patent are that it relates to planar SRAM devices, not Vertical SRAM devices and it does not suggest a process for forming such devices. In addition, the Flaker et al. patent does not provide any guidance as to the kind of process to employ in the manufacture of a vertical SRAM device or the structure of a vertical SRAM device.
There is a problem of providing a Vertical SRAM device without the problems of floating body variations in Vt mismatch which are unreliable since they can destroy data on the one hand or the consumption of surface are of the devices to provide contacts to the bodies of the FET devices to overcome the Vt mismatch problems.
For a DRAM application, such those taught by Forbes et al which teaches at col 12 lines 58–62 thereof that Vt must remain sufficiently high to avoid sub-threshold leakage. Negative wordline (WL) low is not contemplated. There are problems with the scheme used for body contacting in Forbes et al. First, there is a need to align of the body contact precisely vertically with the channel to avoid leakage between the source/drain diffusions and the body contact. Secondly, the presence of the body contact in such close proximity to the gated channel and diffusions may introduce an extremely high carrier recombination velocity due to interfacial defects that would burden transistor operation with significant leakage currents.